The invention relates to a method of manufacturing a semiconductor device with a bipolar transistor and a MOS transistor which are formed in a silicon body which is for this purpose provided with a field insulation region by which semiconductor regions adjoining a surface of the silicon body are mutually insulated, comprising a first region for the bipolar transistor and a second region for the MOS transistor, after which the second region is provided with a gate dielectric and after which an electrode layer of non-crystalline silicon is deposited on the surface, which electrode layer is provided with a doping and in which electrode layer subsequently an emitter electrode is formed on the first region and a gate electrode on the second region.
A semiconductor device with a single bipolar transistor and a single MOS transistor can be manufactured by such a method. In practice, however, the method will be used for the manufacture of a semiconductor device comprising an integrated circuit of a large number of bipolar and MOS transistors. The circuit may then comprise both NPN and PNP bipolar transistors as well as MOS transistors of the N-channel and P-channel type. Such an integrated circuit, which comprises besides bipolar transistors also NMOS and PMOS transistors, is called an integrated BiCMOS circuit.
After the emitter electrode has been formed on the semiconductor region, the emitter zone of the bipolar transistor can be formed from the doped emitter electrode which lies immediately on the surface of the silicon body through diffusion into the base zone. The gate electrode formed on the second region may be utilized, as is usual, as a mask for the implantation of ions for forming source and drain zones of the MOS transistor in the second region.
U.S. Pat. No. 5,089,429 discloses a method of the kind mentioned in the opening paragraph whereby the electrode layer of non-crystalline silicon is provided with a dopant with a concentration of approximately 10.sup.20 dopant atoms per cc immediately after deposition, which concentration is so high that the emitter zone of the transistor can be formed through diffusion from the emitter electrode to be formed in the electrode layer. Then the electrode layer, which is now well conducting, is provided with an insulating top layer and is etched into a pattern with an emitter electrode on the first semiconductor region and a gate electrode on the second semiconductor region.
The electrode layer of non-crystalline silicon is etched into a pattern in an etching plasma with reactive ions (RIE). During the subsequent formation of the source and drain zones of the MOS transistor, ions of a dopant are implanted, the gate electrode being used as a mask. The electrode layer of non-crystalline silicon could become charged locally during these processes. As a result, strong electric fields could locally arise across the very thin gate dielectric layer present below the layer of non-crystalline silicon. The former could be damaged then by electric breakdown: "gate oxide breakdown". The layer of non-crystalline silicon, however, has already been provided with dopant atoms before the etching process and the implantation process are carried out. The layer of non-crystalline silicon is conducting during said processes as a result, whereby any local charging is avoided. Damage to the very thin layer of gate dielectric is prevented thereby.
The entire electrode layer is comparatively heavily doped in the known method. When the method is used for manufacturing a semiconductor device with both NMOS and PMOS transistors, the gate electrodes of both types of MOS transistors will have the same conductivity type. These transistors will accordingly have threshold voltages of different absolute values.
After doping, the layer of non-crystalline silicon is provided with a silicon oxide top layer. The pattern is then etched into this top layer as well as into the layer of non-crystalline silicon during the etching treatment. The top layer remaining on the gate electrodes protects these electrodes during the implantation of dopant atoms for the formation of the source and drain zones. The top layer must be locally removed for external contacting of the gate electrodes. If the gate electrodes are to be provided with a conducting silicide layer in a self-aligned manner, through deposition of a metal layer and a subsequent heat treatment, this top layer should even be entirely removed.